1. Field of the Invention
The present invention is related to delay locked loops (DLLs), and more particularly, to reduction of jitter effects and improvement of link robustness in high-speed transceiver circuits using DLLs.
2. Related Art
DLL (Delay Locked Loop)-based clock and data recovery is widely used in high speed data links. DLL-based clock and data recovery has two clocks. One clock typically comes from external incoming data, and a second clock comes from a local phase locked loop (PLL) with a local reference clock. The DLL extracts clock information from the incoming data and tries to lock the two clocks to each other, using delays. Since there is usually no way to change the local frequency of the PLL, which is locked to the local reference frequency, the variable that can be changed is the phase of the PLL output clock, or, equivalently, the delay. A phase detector used in DLL-based data clock recovery is called a “bi-phase” detector. It uses the clock to sample the data during different phases of the clock to extract the timing information between the incoming data and local sampling clock. For example, it can sample the data in the middle of the symbol (the middle of the “eye”) or towards the end of the symbol. This is then used to compare whether the local clock input is “ahead” or “behind” of the reference clock.
The loop in the DLL can be either an analog loop, or a digital loop. The DLL loop tries to determine whether the clock lags the data or leads the data. The phase of the sample clock is then adjusted accordingly. A phase interpolator is used to change the phase of the sample clock. Thus, the purpose of the phase interpolator is to lock the phase of the clock to the phase of the incoming data.
DLL based timing recovery is particularly popular for serial digital data communication. The advantage of this method is that all timing recovery is performed in digital domain with full programmability. It is specially suitable for multi-channel serial data link applications without interference among multiple on-chip PLLs running at different clock frequencies. A DLL-based timing recovery circuit uses a phase detector (a slicer), a deserializer (DMUX), digital timing recovery circuit and a phase interpolator, as shown in FIG. 1.
FIG. 1 illustrates a conventional DLL-based timing recovery circuit. As shown in FIG. 1, data is received into two D flip flops (DFFs) 102 and 108, which are clocked by the 0° clock and 180° clock, respectively. The DFFs 102, 108 output their outputs to demultiplexers 104, 110, respectively. The demultiplexers 104, 110 output peak data and zero data, respectively, into a digital timing recovery circuit 106. The digital timing recovery circuit 106 outputs phase control bits to a phase interpolator 112, which also takes as input various multiphase clocks, generated from the on-chip PLL locked to the local reference clock. The phase interpolator 112 outputs the 0° clock and the 180° clock waveforms to the DFFs 102, 108, respectively.
Thus, in the circuit of FIG. 1, the phase detector (i.e., the DFFs 102, 108) samples or slices input data at certain clock phase. The deserializer 109, 110 de-multiplexes high-speed serial data to low-speed parallel data. The digital timing recovery circuit 106 extracts timing information from incoming sampled data and sends timing control information to the phase interpolator 112. The phase interpolator 112 adjusts the clock phases accordingly for use by the slicers 102, 108 to sample the data.
The most critical component is the phase detector 102, 108. A typical topology of the phase detector 102, 108 is the “bang/bang” phase detector, embodied in a D flip flop. Its nature of implicit digital output is advantageous for digital signal processing. The phase interpolator 112 produces 0° clock (positive output) and 180° clock (negative or complementary output) to sample the data. When the loop is locked, the 0° clock should sample at the center of the eye and the 180° clock samples at the transition of data. The 0° clock-driven slicer/DMUX 102, 104 creates the data called “peak data” (also referred to as “real data”) and the 180° clock-driven slicer/DMUX 108, 110 creates the data called “zero data” (referred to “zero-crossing point”). FIG. 2 shows the timing diagram at the input slicers 102, 108.
Ideally, the 0° clock waveform falls exactly in the middle of the data symbol, or exactly in the middle of the “eye”. Similarly, the 180° clock waveform also has a transition exactly in the cross point of the eye. However, in practice, the clock phase always moves back and forth. In high-speed data circuits, this is primarily due to the performance of the D flip flops, which is the limiting factor in the DLL performance. Typically, the settling time and holding time of the D flip flops is asymmetric. This means that the sampling point is not optimized to be exactly in the center of the eye. The faster the data rate, the smaller the eye, and therefore the more critical it is to ensure that the 0° clock falls exactly in the center of the eye. Conventionally, moving the 0° clock transitions relative to the data has been difficult. This is due partly because of the high gain of the DLL loop, and partly because of the pattern-dependence of the phase detector. This can result in pattern-dependent jitter.
Thus, even with today's modern process technology, the settling/hold time of DFF is still a limiting factor for overall system performance, especially when incoming data has a lot of timing jitter. The imbalance between the settling time and hold time for a typical DFF can erode the limited timing margin of phase detector. Another important reason for phase adjustment is that the incoming data with non-Gaussian or asymmetric distributed timing jitter or ISI (Inter-Symbol Interference) will cause the locked sampling clock off the center of open eye due to the averaging nature of loop. Thus, phase adjustment is necessary for optimal sampling point. Meanwhile, phase adjustment can also provide the system level information of quality of incoming data by checking BER (Bit Error Rate) at different sampling points of the incoming data. A way to address phase adjustment is to put phase offset on phase interpolator in digital loop. Because of the data pattern-dependent nature of phase detector and the loop trying to compensate the offset by moving both sampling points, the phase adjustment may not achieve a stable sampling point or suffer pattern-dependent behavior.
Accordingly, there is a need in the art for a DLL with improved jitter performance.